How to run testbench.v with verilator Running Verilog Testbenches with Verilator A Comprehensive Guide Verilator is a powerful open source tool used for simulating Verilog and System Verilog designs 2 min read 04-10-2024 35
How to do matrix transpose using RVV1.0? Accelerating Matrix Transpose with RISC V Vector Extensions RVV 1 0 Matrix transpose is a fundamental operation in linear algebra frequently used in various app 2 min read 04-10-2024 45
Effective trace algorithm created 3 traps as response to 2 exceptions Understanding Trace Algorithms Managing Exceptions with Effective Traps In the world of programming managing exceptions efficiently is crucial for maintaining r 2 min read 30-09-2024 43
Self build toolchains for RISC-V lacking correct libc Self Build Toolchains for RISC V Lacking Correct Libc Understanding the Problem Creating self build toolchains for RISC V architecture can be a challenging ende 3 min read 24-09-2024 70
ESP32-H2 Risc-V cpu extensions Exploring ESP 32 H2 RISC V CPU Extensions The ESP 32 H2 is an advanced microcontroller developed by Espressif featuring the RISC V architecture and designed for 2 min read 24-09-2024 47
Exception RISCV APB Understanding Exceptions in RISC V APB In this article we will delve into the concept of exceptions in the RISC V architecture specifically focusing on the Adva 2 min read 14-09-2024 52
How do I write NOT Operation for the Risc-V (Assembly Language)? How to Write a NOT Operation in RISC V Assembly Language In computer science the NOT operation is a fundamental unary operation that inverts the bits of its ope 2 min read 14-09-2024 94
GCC Compile-time switch for floating point support? Understanding GCC Compile Time Switch for Floating Point Support When working with GCC GNU Compiler Collection developers may need to decide on floating point s 2 min read 14-09-2024 62
Writing to qemu RISCV UART using c Writing to the QEMU RISC V UART using C A Step by Step Guide Trying to communicate with the UART in QEMU using your RISC V code can be a bit tricky but its esse 3 min read 13-09-2024 60
CH32V203 Jumping to bootloader from software Jumping to the Bootloader on the CH 32 V203 from Software The CH 32 V203 a RISC V microcontroller from Giga Device offers a powerful and flexible approach to fi 3 min read 03-09-2024 58
How to cross complie libudev without building systemd?? Trouble using meson? Building libudev Without Systemd A Cross Compilation Journey This article explores the challenge of cross compiling libudev without building the entire systemd 3 min read 03-09-2024 68
Creating an array at specific address with predefined size Creating an Array at a Specific Address in Embedded Systems RISC V This article explores the challenges and solutions involved in creating an array at a specifi 3 min read 02-09-2024 54
Converting ARM assembly to RISC-V assembly Converting ARM Assembly to RISC V A Practical Guide Converting assembly code between different architectures like ARM and RISC V can be tricky especially for be 3 min read 02-09-2024 72
Cannot stepi into ecall in xv6 Debugging Xv6 Why Cant I Step into ecall in GDB Stepping into system calls in Xv6 can be a powerful debugging technique allowing you to understand how the kerne 2 min read 01-09-2024 56
Restoring riscv64 machine using a full backup Restoring a RISC V Machine Using a Full Backup A Comprehensive Guide This article delves into the process of restoring a RISC V machine specifically the Lichee 2 min read 01-09-2024 50
RVV type for a class member in C++ RVV Types in C Class Members A Guide to Vector Extensions The RISC V Vector Extension RVV offers significant performance enhancements for vectorized operations 3 min read 01-09-2024 53
what openOCD does to spike while debugging a program with spike? Decoding the Spike Debugger Understanding Open OCD and Memory Modifications This article delves into the workings of the Spike debugger specifically focusing on 2 min read 01-09-2024 58
build the gcc5.4 in riscv, but rising the error that unknown mode 'TF' Unknown Mode TF Troubleshooting GCC 5 4 on RISC V Building GCC 5 4 for the RISC V architecture can be challenging especially when encountering cryptic errors li 2 min read 01-09-2024 54
RISC-V assembly: global pointer set to a weird value RISC V Assembly Unraveling the Mystery of the Global Pointer This article investigates a common issue faced by RISC V assembly programmers an unexpected value i 3 min read 31-08-2024 50
llama run on qemu-riscv64 with and without vector extension Running L La MA on QEMU RISC V with and Without Vector Extensions A Detailed Guide Large language models LLMs like L La MA are revolutionizing the field of natu 3 min read 30-08-2024 46
RISC V : I don't understand what the GNU assembler does with labels in the .data segment Understanding Label Addressing in RISC V Assembly with GNU Assembler This article explores a common confusion when working with labels within the data segment i 2 min read 29-08-2024 51
Error with riscv-gnu-toolchain: "listing the stack pointer register 'sp' in a clobber list is deprecated" Understanding the listing the stack pointer register sp in a clobber list is deprecated error in riscv gnu toolchain The error listing the stack pointer registe 2 min read 28-08-2024 59
CH32V003 Auto-wakeup Window Comparison Value Register problem Understanding the CH 32 V003 Auto wakeup Window Comparison Value Register Problem The CH 32 V003 microcontroller a RISC V device uses the Auto wakeup Window Com 2 min read 28-08-2024 42
format of RISCV instruction encoding in Spike? Demystifying RISC V Instruction Encoding in Spike Understanding how instructions are encoded in a RISC V processor like Spike is crucial for developers working 3 min read 28-08-2024 57
Is is possible to Connect one Master port to multiple Slave ports in GEM5? Connecting a Master Port to Multiple Slave Ports in GEM 5 Understanding the Problem The error message you are encountering fatal Port lvsram0 m0 port is already 2 min read 27-08-2024 60